The present invention relates a liquid crystal display device or other active matrix type display device and a mobile terminal using the same.
In recent years, mobile phones, personal digital assistants (PDAs), and other mobile terminals have rapidly spread in use. One of the factors behind the rapid spread of these mobile terminals has been the liquid crystal display devices provided as the display areas of their outputs. The reason is that liquid crystal display devices are displays by nature not in principle requiring power for being driven and therefore having a low power consumption.
In recent years, active matrix type display devices using polysilicon thin film transistors (TFTs) as switching elements of pixels have had digital interface drive circuits formed integrally on the same substrates as display areas comprised of pixels arranged in a matrix. In such an integral drive circuit type display device, a horizontal drive system and a vertical drive system are arranged at the periphery (frame) of the active display area. These drive systems are integrally formed on the same substrate together with the pixel area by using polysilicon TFTs.
FIG. 1 is a diagram showing the schematic configuration of a general integral drive circuit type display device (see for example Japanese Unexamined Patent Publication (Kokai) No. 2002-175033).
This liquid crystal display device, as shown in FIG. 1, is comprised of a transparent insulating substrate, for example, a glass substrate 1, on which an active display area 2 comprised of a plurality of pixels including liquid crystal cells arranged in a matrix, a pair of horizontal drive circuits (H drivers) 3U and 3D arranged above and below the active display area 2 in FIG. 1, a vertical drive circuit (V driver) 4 arranged at a side part of the active display area 1 in FIG. 1, one reference voltage generation circuit 5 for generating a plurality of reference voltages, and a data processing circuit 6 are formed.
In this way, the integral drive circuit type display device of FIG. 1 has two horizontal drive circuits 3U and 3D arranged at both sides of the active display area 2 (above and below in FIG. 1). This is for driving the display while dividing data lines to odd number lines and even number lines.
FIG. 2 is a block diagram showing an example of the configuration of the horizontal drive circuits 3U and 3D of FIG. 1 for separately driving the odd number lines and the even number lines.
As shown in FIG. 2, the horizontal drive circuit 3U for driving the odd number lines and the horizontal drive circuit 3D for driving the even number lines have the same configuration. Specifically, they have shift register (HSR) groups 3HSRU and 3HSRD for sequentially outputting shift pulses (sampling pulses) from transfer stages in synchronization with a horizontal transfer clock HCK (not shown), sampling latch circuit groups 3SMPLU and 3SMPLD for sequentially sampling and latching digital image data by sampling pulses given from shift registers 31U and 31D, line sequence latch circuit groups 3LTCU and 3LTCD for arranging latch data of the sampling latch circuits 32U and 32D in line sequence, and digital/analog conversion circuit (DAC) groups 3DACU and 3DACD for converting the digital image data arranged in line sequence in the line sequence latch circuits 33U and 33D to analog image signals. Note that, usually, level shift circuits are arranged at input stages of the DACs 34U and 34D and level upped data are input to the DACs 34U and 34D.
As shown in FIG. 2, the horizontal drive circuits 3U and 3D of FIG. 1 have sampling latch circuits 32, line sequence latch circuits 33, and DACs 34 arranged for each odd number data line and even number data line to be driven.
Further, in mobile phones and other mobile terminals, there has been increasingly stronger demand for lowering the power consumption of the display device along with their rapid spread. Particularly, the reduction of the power consumption in the standby period has become an important point in increasing the battery life, so has become a particularly strong requirements. A variety of power saving technologies have been proposed for this requirement. As one of them, the so-called “1 bit mode” (2 gradation mode) of restricting the number of gradation of the image display to “2” (1 bit) for each color at the time of standby is known. In this 1 bit mode, gradations are expressed by 1 bit per color, therefore images are displayed by a total of eight colors.
However, in the horizontal drive circuit of FIG. 2 explained above, one data line requires 1 set of a sampling latch circuit 32, line sequence latch circuit 33, and DAC 34, therefore the lateral width permitted in terms of layout is small. For this reason, reduction of the pitch is impossible. Further, there is the disadvantage that the number of required circuits is large, therefore the frame becomes large. In the case of the horizontal drive circuits of FIG. 2, three sampling latch circuits for sampling serial/parallel converted R (red), G (green), and B (blue) data are required. With this, it is difficult to meet the demands for narrower pitch and narrower frame. In order to overcome this, it can be also considered to extend the layout in the vertical direction, but this abruptly increases the layout area and makes realization of a narrower frame difficult.
Further, as the DACs, ones of the reference voltage selection type are employed, but the same color is divided vertically by even number columns and odd number columns. Therefore, unless the output potentials of the reference voltage generation circuits 15 are made the same, vertical stripes etc. will be generated, so it is necessary to connect reference voltage lines RVL of the DACs 34U and 34D of the two horizontal drive circuits 3U and 3D. For this reason, an increase of the frame in the lateral direction in FIG. 1 is induced.
Further, in a display device having an 8 color mode (low gradation mode), usually two DACs, one for the normal mode and one for the 8 color mode, are provided. The two DACs, however, shared the sampling latch circuit and the line sequential alignment circuit. Both at the time of the normal mode and at the time of the 8 color mode, the level was converted, then the data was input to the DACs. For this reason, there were the following disadvantages. At the time of the 8 color mode as well, the DAC input signal is made large in amplitude, therefore the charged/discharged current is large and the power consumption is high. Further, the higher bit and lower bit level shifter circuits are separately processed, therefore the circuit of the latch portion becomes large, and the frame becomes large.